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LTC3814-5 60V Current Mode Synchronous Step-Up Controller FEATURES
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DESCRIPTION
The LTC3814-5 is a synchronous step-up switching regulator controller that can generate output voltages up to 60V. The LTC3814-5 uses a constant off-time peak current control architecture to deliver very high duty cycles with accurate cycle-by-cycle current limit without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifier provides very fast line and load transient response. Large 1 gate drivers allow the LTC3814-5 to drive large power MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN. A shutdown pin allows the LTC3814-5 to be turned off reducing the supply current to <230A.
PARAMETER Maximum VOUT MOSFET Gate Drive INTVCC UV + INTVCC UV - LTC3813 100V 6.35V to 14V 6.2V 6V LTC3814-5 60V 4.5V to 14V 4.2V 4V
High Output Voltages: Up to 60V Large 1 Gate Drivers No Current Sense Resistor Required Dual N-Channel MOSFET Synchronous Drive 0.5% 0.8V Voltage Reference Fast Transient Response Programmable Soft-Start Generates 5.5V Driver Supply Power Good Output Voltage Monitor Adjustable Off-Time/Frequency: tOFF(MIN) < 100ns Adjustable Cycle-by-Cycle Current Limit Undervoltage Lockout On Driver Supply Output Overvoltage Protection Thermally Enhanced 16-Pin TSSOP Package
APPLICATIONS
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24V Fan Supplies 48V Telecom and Base Station Power Supplies Networking Equipment, Servers Automotive and Industrial Control Systems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.
TYPICAL APPLICATION
High Efficiency High Voltage Step-Up Converter
100
VOUT 263k IOFF 100k PGOOD PGOOD VRNG VOFF RUN/SS 1000pF 0.01F 100k VFB 100pF SGND ITH BG PGND 1F 1k BOOST TG 0.1F SW EXTVCC INTVCC D1 MBR1100 M2 Si7848DP 29.4k 4.7H LTC3814-5 M1 Si7848DP VOUT 24V 4A NDRV VIN 4.5V TO 14V 22F
Efficiency vs Load Current
VIN = 12V 95 EFFICIENCY (%)
+
90
VIN = 5V
85
+
270F x2
80
0
1
2 LOAD (A)
3
38145 TA01b
4
38145 TA01
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LTC3814-5 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW IOFF VOFF VRNG PGOOD ITH VFB RUN/SS SGND 1 2 3 4 5 6 7 8 17 16 BOOST 15 TG 14 SW 13 PGND 12 BG 11 INTVCC 10 EXTVCC 9 NDRV
Supply Voltages INTVCC ................................................... -0.3V to 14V (INTVCC - PGND), (BOOST - SW) ......... -0.3V to 14V BOOST (Continuous) ............................. -0.3V to 85V BOOST (400ms) .................................. -0.3V to 95V EXTVCC .................................................. -0.3V to 15V (EXTVCC - INTVCC).................................. -12V to 12V (NDRV - INTVCC) Voltage........................... -0.3V to 10V SW Voltage (Continuous).............................. -1V to 70V SW Voltage (400ms) ..................................... -1V to 80V IOFF Voltage (Continuous) .......................... -0.3V to 70V IOFF Voltage (400ms) ................................. -0.3V to 80V RUN/SS Voltage ........................................... -0.3V to 5V PGOOD Voltage ............................................ -0.3V to 7V VRNG, VOFF Voltages ................................... -0.3V to 14V FB Voltage ................................................. -0.3V to 2.7V TG, BG, INTVCC, EXTVCC RMS Currents .................50mA Operating Temperature Range (Note 2) LTC3814E-5 ......................................... -40C to 85C LTC3814I-5 ........................................ -40C to 125C Junction Temperature (Notes 3, 7)........................ 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 38C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3814EFE-5#PBF LTC3814IFE-5#PBF TAPE AND REEL LTC3814EFE-5#TRPBF LTC3814IFE-5#TRPBF PART MARKING 3814EFE-5 3814IFE-5 PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP TEMPERATURE RANGE -40C to 85C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC3814-5 ELECTRICAL CHARACTERISTICS
SYMBOL Main Control Loop INTVCC IQ IBOOST VFB INTVCC Supply Voltage INTVCC Supply Current INTVCC Shutdown Current BOOST Supply Current Feedback Voltage RUN/SS > 1.5V (Notes 4, 5) RUN/SS = 0V RUN/SS > 1.5V (Note 5) RUN/SS = 0V (Note 4) 0C to 85C -40C to 85C -40C to 125C (I-grade) 5V < INTVCC < 14V (Note 4) VRNG = 2V, VFB = 0.76V VRNG = 0V, VFB = 0.76V VRNG = INTVCC, VFB = 0.76V VRNG = 2V, VFB = 0.84V VRNG = 0V, VFB = 0.84V VRNG = INTVCC, VFB = 0.84V VFB = 0.8V 65 (Note 6) 0.6 RUN/SS = 0V INTVCC Rising Hysteresis IOFF = 100A IOFF = 300A IOFF = 2000A 350 VBG = 0V VTG - VSW = 0V 0.7 0.7 1 1 1 1 VFB Rising VFB Falling VFB Returning IPGOOD = 5mA VPGOOD = 5V 7.5 -7.5 10 -10 1.5 0.3 0 1.5 12.5 -12.5 3 0.6 2 1.5
l l l l l l
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, INTVCC = VBOOST = VRNG = VEXTVCC = VNDRV = VOFF = 5V, unless otherwise specified.
PARAMETER CONDITIONS MIN 4.35 3 224 240 0 0.796 0.794 0.792 0.792 256 70 170 0.800 0.800 0.800 0.800 0.002 320 95 215 -300 -85 -200 20 100 25 0.9 1.4 4.2 0.5 1.85 605 1.2 2.5 4.35 150 TYP MAX 14 6 600 400 5 0.804 0.806 0.806 0.808 0.02 384 120 260 UNITS V mA A A A V V V V %/V mV mV mV mV mV mV nA dB MHz V A V V s ns ns ns A A % % % V A
VFB,LINE VSENSE(MAX)
Feedback Voltage Line Regulation Maximum Current Sense Threshold
VSENSE(MIN)
Minimum Current Sense Threshold
IVFB AVOL(EA) fU VRUN/SS IRUN/SS VVCCUV Oscillator tOFF tOFF(MIN) tON(MIN) Driver IBG,PEAK RBG,SINK ITG,PEAK RTG,SINK PGOOD Output VFBOV VFB,HYST VPGOOD IPGOOD
Feedback Current Error Amplifier DC Open-Loop Gain Error Amp Unity Gain Crossover Frequency Shutdown Threshold RUN/SS Source Current INTVCC Undervoltage Lockout
0.7 4.05
Off-Time Minimum Off-Time Minimum On-Time BG Driver Peak Source Current BG Driver Pulldown RDS(ON) TG Driver Peak Source Current TG Driver Pulldown RDS(ON) PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis PGOOD Low Voltage PGOOD Leakage Current
1.55 515
2.15 695 100
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LTC3814-5 ELECTRICAL CHARACTERISTICS
SYMBOL PG Delay VCC Regulators VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising EXTVCC Hysteresis INTVCC Voltage from EXTVCC VEXTVCC - VINTVCC at Dropout INTVCC Load Regulation from EXTVCC INTVCC Voltage from NDRV Regulator INTVCC Load Regulation from NDRV Current into NDRV Pin Maximum Supply Voltage Maximum Current into NDRV/INTVCC 6V < VEXTVCC < 15V ICC = 20mA, VEXTVCC = 5V ICC = 0mA to 20mA, VEXTVCC = 10V Linear Regulator in Operation ICC = 0mA to 20mA, VEXTVCC = 0 VNDRV - VINTVCC = 3V Trickle Charger Shunt Regulator Trickle Charger Shunt Regulator, INTVCC 16.7V (Note 8) 10 20 5.2
l
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, INTVCC = VBOOST = VRNG = VEXTVCC = VNDRV = VOFF = 5V, unless otherwise specified.
PARAMETER PGOOD Delay CONDITIONS VFB Falling MIN TYP 125 MAX UNITS s
4.5 0.1 5.2
4.7 0.25 5.5 75 0.01 5.5 0.01 40 15
0.4 5.8 150 5.8 60
V V V mV % V % A V mA
VINTVCC,1 VEXTVCC,1 VLOADREG,1 VINTVCC,2 VLOADREG,2 INDRV VCCSR ICCSR
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3814E-5 is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3814I-5 is guaranteed to meet performance specifications over the full -40C to 125C operating temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3814-5: TJ = TA + (PD * 38C/W)
Note 4: The LTC3814-5 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 1V and 2V. Note 5: The dynamic input supply current is higher due to the power MOSFET gate charging being delivered at the switching frequency (QG * fSW). Note 6: Guaranteed by design. Not subject to test. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: ICC is the sum of current into NDRV and INTVCC.
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response
VOUT 200mV/DIV
Start-Up
VOUT 10V/DIV
Overcurrent Operation
VOUT 10V/DIV RUN/SS 4V/DIV
IOUT 2A/DIV
38145 G01
IL 5A/DIV
IL 5A/DIV 100s/DIV FRONT PAGE CIRCUIT VIN = 12V 0A TO 4A LOAD STEP 1ms/DIV FRONT PAGE CIRCUIT VIN = 12V ILOAD = 1A
38145 G02
200s/DIV FRONT PAGE CIRCUIT VRNG = 1V VIN = 12V RSHORT = 1
38145 G03
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LTC3814-5 TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
100 VOUT = 50V 300 VIN = 36V VIN = 24V FREQUENCY (kHz) VIN = 12V 90 280 FREQUENCY (kHz) ILOAD = 0A 260 ILOAD = 1A 240
Frequency vs Input Voltage
FRONT PAGE CIRCUIT 300
Frequency vs Load Current
FRONT PAGE CIRCUIT
95 EFFICIENCY (%)
280
VIN = 12V
260
240 VIN = 5V 220
85 220
80
0
1
2
3
4
5
38145 G04
200
5
7
LOAD (A)
11 9 INPUT VOLTAGE (V)
13
15
38145 G05
200
0
1
3 2 LOAD CURRENT (A)
4
38145 G06
ITH Voltage vs Load Current
3 CURRENT SENSE THRESHOLD (mV) FRONT PAGE CIRCUIT VIN = 12V VRNG = 1V 400 300 200 100 0 -100 -200 -300 -400
Current Sense Threshold vs ITH Voltage
10000 VRNG = 2V 1.4V OFF-TIME (ns) 1V 0.7V 0.5V 1000
Off-Time vs IOFF Current
VOFF = INTVCC
ITH VOLTAGE (V)
2
1
100
0
0
1
2
3
4
5
38145 G07
10 0 0.5 1 1.5 2 ITH VOLTAGE (V) 2.5 3
38145 G08
10
LOAD CURRENT (A)
100 1000 IOFF CURRENT (A)
10000
38145 G09
Off-Time vs Temperature
MAXIMUM CURRENT SENSE THRESHOLD (mV) 680 660 640 620 600 580 560 -50 -25 IOFF = 300A 400
Maximum Current Sense Threshold vs VRNG Voltage
MAXIMUM CURRENT SENSE THRESHOLD (mV) 240
Maximum Current Sense Threshold vs Temperature
VRNG = INTVCC 230
300
OFF-TIME (ns)
220
200
210
100
200
50 25 75 0 TEMPERATURE (C)
100
125
38145 G10
0 0.5
1
1.5
2
38145 G11
190 -50
-25
VRNG VOLTAGE (V)
50 25 0 75 TEMPERATURE (C)
100
125
38145 G12
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LTC3814-5 TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage vs Temperature
0.803 0.802 REFERENCE VOLTAGE (V) 0.801 0.800 0.799 0.798 0.797 -50 0.5 -50 1.5
Driver Peak Source Current vs Temperature
VBOOST = VINTVCC = 5V 1.75 1.50 1.25 1.0 RDS(ON) () 1.00 0.75 0.50
Driver Pulldown RDS(ON) vs Temperature
VBOOST = VINTVCC = 5V
PEAK SOURCE CURRENT (A)
-25
50 25 0 75 TEMPERATURE (C)
100
125
-25
0 25 50 75 TEMPERATURE (C)
100
125
0.25 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
38145 G14
38145 G15
38145 G16
Driver Peak Source Current vs Supply Voltage
3.0 2.5 2.0 RDS(ON) () 0.9 1.5 1.0 0.5 0 0.7 1.1
Driver Pulldown RDS(ON) vs Supply Voltage
7 6 1.0 RESISTANCE () 5 4 3 2 1
EXTVCC Switch Resistance vs Temperature
PEAK SOURCE CURRENT (A)
0.8
0.6 4 5 6 7 8 9 10 11 12 13 14 DRVCC /BOOST VOLTAGE (V)
38145 G17
4
5
6 7 8 9 10 11 12 13 14 DRVCC /BOOST VOLTAGE (V)
38145 G21
0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
38145 G19
INTVCC Current vs Temperature
5 INTVCC = 5V 4 INTVCC CURRENT (mA) INTVCC CURRENT (A) 400
INTVCC Shutdown Current vs Temperature
INTVCC = 5V
300
3
200
2
100
1
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
0 -50 -25
0
75 50 25 TEMPERATURE (C)
100
125
38145 G20
38145 G21
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LTC3814-5 TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Current vs INTVCC Voltage
3.5 3.0 INTVCC CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 0 0 2 8 6 10 4 INTVCC VOLTAGE (V) 12 14 INTVCC CURRENT (A) 350 300 250 200 150 100 50 0 0 2 8 6 10 4 INTVCC VOLTAGE (V) 12 14
INTVCC Shutdown Current vs INTVCC Voltage
38145 G22
38145 G23
RUN/SS Pull-Up Current vs Temperature
3 RUN/SS = 0V SHUTDOWN THRESHOLD (V) 2.2 2.0 SS/TRACK CURRENT (A) 1.8 1.6 1.4 1.2 1.0 0.8 0 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125
Shutdown Threshold vs Temperature
2
1
0.6 -50 -25
0
75 50 25 TEMPERATURE (C)
100
125
38145 G24
38145 G25
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LTC3814-5 PIN FUNCTIONS
IOFF (Pin 1): Off-Time Current Input. Tie a resistor from VOUT to this pin to set the one-shot timer current and thereby set the switching frequency. VOFF (Pin 2): Off-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to an external resistive divider from the input makes the off-time proportional to VIN. The comparator defaults to 0.7V when the pin is grounded and defaults to 2.4V when the pin is connected to INTVCC. VRNG (Pin 3): Sense Voltage Limit Set. The voltage at this pin sets the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 95mV when this pin is tied to ground, and 215mV when tied to INTVCC. PGOOD (Pin 4): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not between 10% of the regulation point. The output voltage must be out of regulation for at least 125s before the power good output is pulled to ground. ITH (Pin 5): Error Amplifier Compensation Point and Current Control Threshold. The current comparator threshold increases with control voltage. The voltage ranges from 0V to 2.6V with 1.2V corresponding to zero sense voltage (zero current). VFB (Pin 6): Feedback Input. Connect VFB through a resistor divider network to VOUT to set the output voltage. RUN/SS (Pin 7): RUN/Soft-Start Input. For soft-start, a capacitor to ground at this pin sets the ramp rate of the maximum current sense threshold. Pulling this pin below 0.9V will shut down the LTC3814-5, turn off both of the external MOSFET switches and reduce the quiescent supply current to 224A. SGND (Pin 8): Signal Ground. All small-signal components should connect to this ground and eventually connect to PGND at one point. NDRV (Pin 9): Drive Output for External Pass Device of the Linear Regulator for INTVCC. Connect to the gate of an external NMOS pass device and a pull-up resistor to the input voltage VIN or the output voltage VOUT. EXTVCC (Pin 10): External Driver Supply Voltage. When this voltage exceeds 4.7V, an internal switch connects this pin to INTVCC through an LDO and turns off the external MOSFET connected to NDRV, so that controller and gate drive are drawn from EXTVCC. INTVCC (Pin 11): Main Supply and Driver Supply Pin. All internal circuits and bottom gate output driver are powered from this pin. INTVCC should be bypassed to SGND and PGND with a low ESR (X5R or better) 1F capacitor in close proximity to the LTC3814-5. BG (Pin 12): Bottom Gate Drive. The BG pin drives the gate of the bottom N-channel main switch MOSFET. This pin swings from PGND to INTVCC. PGND (Pin 13): Bottom Gate Return. This pin connects to the source of the pull-down MOSFET in the BG driver and is normally connected to ground. SW (Pin 14): Switch Node Connection to Inductor and Bootstrap Capacitor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VOUT. TG (Pin 15): Top Gate Drive. The TG pin drives the gate of the top N-channel synchronous switch MOSFET. The TG driver draws power from the BOOST pin and returns to the SW pin, providing true floating drive to the top MOSFET. BOOST (Pin 16): Top Gate Driver Supply. The BOOST pin supplies power to the floating TG driver. BOOST should be bypassed to SW with a low ESR (X5R or better) 0.1F capacitor. An additional fast recovery diode from INTVCC to the BOOST pin will create a complete floating chargepumped supply at BOOST. Exposed Pad (Pin 17): Ground. The Exposed Pad must be soldered to PCB ground.
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LTC3814-5 FUNCTIONAL DIAGRAM
VIN 5.5V
+ -
OFF
NDRV 9 M3
INTVCC 11 EXTVCC 10
INTVCC
5V REG
0.8V REF
+ -
INTVCC
VIN VOFF 2
UV
-
ON 4.2V
5.5V
+
+
+ -
4.7V
DB
VIN
BOOST ROFF IOFF 1 16 VVOFF tOFF = (76pF) IIOFF TG R S Q ON 15 SW 14 OVERTEMP SENSE SHDN SWITCH LOGIC M1 INTVCC OV BG 12 PGND CVCC M2 CB L
+
CIN
VOUT
+
ICMP
20k
VOUT
-
x
1.4V VRNG 3 FAULT ITH 5 CC2 RC CC1 2.6V 0.7V 1.4A RUN SHDN UV
13 PGOOD 4
+
COUT
+ -
OV
RFB1 0.72V
EA
0.8V 7
+
4V RUN/SS
+ - - +
-
VFB 6
0.9V
+ -
0.88V SGND 8
RFB2
38145 FD
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LTC3814-5 OPERATION
Main Control Loop The LTC3814-5 is a current mode controller for DC/DC step-up converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer (OST). When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the PGND and SW pins using the bottom MOSFET on-resistance. The voltage on the ITH pin sets the comparator threshold corresponding to the inductor peak current. The fast 25MHz error amplifier EA adjusts this voltage by comparing the feedback signal VFB to the internal 0.8V reference voltage. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. The operating frequency is determined implicitly by the top MOSFET on-time (tOFF) and the duty cycle required to maintain regulation. The one-shot timer generates a top MOSFET on-time that is inversely proportional to the IOFF current and proportional to the VOFF voltage. Connecting VOUT to IOFF and VIN to VOFF with a resistive divider keeps the frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor ROFF. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Forcing a voltage above 0.9V will turn on the device. Fault Monitoring/Protection Constant off-time current mode architecture provides accurate cycle-by-cycle current limit protection--a feature that is very important for protecting the high voltage power supply from output overcurrent conditions. The cycle-by-cycle current monitor guarantees that the inductor current will never exceed the value programmed on the VRNG pin. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a 10% window around the regulation point after the internal 125s power bad mask timer expires. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on immediately and held on until the overvoltage condition clears. The LTC3814-5 provides an undervoltage lockout comparator for the INTVCC supply. The INTVCC UV threshold is 4.2V to guarantee that the MOSFETs have sufficient gate drive voltage before turning on. If INTVCC is under the UV threshold, the LTC3814-5 is shut down and the drivers are turned off. Strong Gate Drivers The LTC3814-5 contains very low impedance drivers capable of supplying amps of current to slew large MOSFET gates quickly. This minimizes transition losses and allows paralleling MOSFETs for higher current applications. A 60V floating high side driver drives the topside MOSFET and a low side driver drives the bottom side MOSFET (see Figure 1). The bottom side driver is supplied directly from the INTVCC pin. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode from INTVCC when the top MOSFET turns off. In an output overvoltage condition, where it is possible that the bottom MOSFET will be off for an extended period of time, an internal timeout guarantees that the bottom MOSFET is turned on at least once every 25s for one top MOSFET on-time period to refresh the bootstrap capacitor.
VIN INTVCC
+
CIN DB BOOST TG SW VOUT BG M1 M2 CB L
LTC3814-5
INTVCC
+
COUT
38145 F01
PGND
Figure 1. Floating TG Driver Supply and Negative BG Return
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LTC3814-5 OPERATION
IC/Driver Supply Power The LTC3814-5's internal control circuitry and top and bottom MOSFET drivers operate from a supply voltage (INTVCC pin) in the range of 4.5V to 14V. If the input supply voltage or another available supply is within this voltage range it can be used to supply IC/driver power. If a supply in this range is not available, two internal regulators are available to generate a 5.5V supply from the input or output. An internal low dropout regulator is good for voltages up to 15V, and the second, a linear regulator controller, controls the gate of an external NMOS to generate the 5.5V supply. Since the NMOS is external, the user has the flexibility to choose a BVDSS as high as necessary.
APPLICATIONS INFORMATION
The basic LTC3814-5 application circuit is shown on the first page of this data sheet. External component selection is primarily determined by the maximum input voltage and load current and begins with the selection of the power MOSFET switches. The LTC3814-5 uses the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Next, COUT is selected for its ability to handle the large RMS current and is chosen with low enough ESR to meet the output voltage ripple and transient specification. Finally, loop compensation components are selected to meet the required transient/phase margin specifications. Duty Cycle Considerations For a boost converter, the duty cycle of the main switch is: VIN(MIN) V D = 1- IN ; DMAX = 1- VOUT VOUT The maximum VOUT capability of the LTC3814-5 is inversely proportional to the minimum desired operating frequency and minimum off-time: VOUT(MAX) = VIN(MIN) f MIN * tOFF(MIN) 60V input in order to dimension the power MOSFET properly and to choose the maximum sense voltage. Based on the fact that, ideally, the output power is equal to the input power, the maximum average input current and average inductor current is: IO(MAX) IIN(MAX) =IL,AVG(MAX) = 1- DMAX The current mode control loop will not allow the inductor peak to exceed VSENSE(MAX)/RSENSE. In practice, one should allow some margin for variations in the LTC38145 and external component values, and a good guide for selecting the maximum sense voltage when VDS sensing is used is: 1.7 * RDS(ON) *IO(MAX) VSENSE(MAX) = 1- DMAX VSENSE is set by the voltage applied to the VRNG pin. Once VSENSE is chosen, the required VRNG voltage is calculated to be: VRNG = 5.78 * (VSENSE(MAX) + 0.026) An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 60mV to 320mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 95mV or 215mV, respectively.
Maximum Sense Voltage and the VRNG Pin The control circuit in the LTC3814-5 measures the input current by using the RDS(ON) of the bottom MOSFET or by using a sense resistor in the bottom MOSFET source, so the output current needs to be reflected back to the
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LTC3814-5 OPERATION
Power MOSFET Selection The LTC3814-5 requires two external N-channel power MOSFETs, one for the bottom (main) switch and one for the top (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage BVDSS, threshold voltage V(GS)TH, on-resistance RDS(ON), Miller capacitance and maximum current IDS(MAX). Since the bottom MOSFET is used as the current sense element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: R RDS(ON)(MAX) = SENSE T The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature (see Figure 2) and typically varies from 0.4%/C to 1.0%/C depending on the particular MOSFET used. ing its off-time and must be chosen with the appropriate breakdown specification. The LTC3814-5 is designed to be used with a 4.5V to 14V gate drive supply (INTVCC pin) for driving logic-level MOSFETs (VGS(MIN) 4.5V). For maximum efficiency, on-resistance RDS(ON) and input capacitance should be minimized. Low RDS(ON) minimizes conduction losses and low input capacitance minimizes transition losses. MOSFET input capacitance is a combination of several components but can be taken from the typical "gate charge" curve included on most data sheets (Figure 3).
VOUT MILLER EFFECT a QIN CMILLER = (QB - QA)/VDS b VGS V
VGS
+
+V DS -
38145 F03
-
Figure 3. Gate Charge Characteristic
2.0
1.5
1.0
0.5
0 -50
50 100 0 JUNCTION TEMPERATURE (C)
150
38145 F02
Figure 2. RDS(ON) vs Temperature
The most important parameter in high voltage applications is breakdown voltage BVDSS. Both the top and bottom MOSFETs will see full output voltage plus any additional ringing on the switch node across its drain-to-source dur-
The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included.
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T NORMALIZED ON-RESISTANCE
LTC3814-5 APPLICATIONS INFORMATION
When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT - VIN VOUT VIN VOUT Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. The LTC3814-5 contains large low impedance drivers capable of driving large gate capacitances without significantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (10 or less) to reduce noise and EMI caused by the fast transitions. Operating Frequency PMAIN = DMAX + IO(MAX) 1 DMAX
2
Synchronous Switch Duty Cycle =
The power dissipation for the main and synchronous MOSFETs at maximum output current are given by:
(
T )RDS(ON)
IO(MAX) 1 (RDR )(CMILLER ) VOUT 2 2 1 DMAX
The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC3814-5 applications is determined implicitly by the one-shot timer that controls the on-time tOFF of the synchronous MOSFET switch. The on-time is set by the current into the IOFF pin and the voltage at the VOFF pin according to: V tOFF = VOFF ( 76pF ) IIOFF Tying a resistor ROFF from VOUT to the IOFF pin yields a synchronous MOSFET on-time inversely proportional to VOUT. This results in the following operating frequency and also keeps frequency constant as VOUT ramps up at start-up: VIN f= (Hz) VVOFF * ROFF (76pF) The VOFF pin can be connected to INTVCC or ground or can be connected to a resistive divider from VIN. The VOFF pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the oneshot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. Note, however, that if the VOFF pin is connected to a constant voltage, the operating frequency will be proportional to the input voltage VIN. Figures 4a and 4b illustrate how ROFF relates to switching frequency as a function of the input voltage and VOFF voltage. To hold frequency constant for input
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1 1 (f) * + INTVCC - VTH(IL) VTH(IL) PSYNC = 1 (IO(MAX) )2( 1 DMAX
T ) RDS(0N)
where T is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2 at VGS = VMILLER). VTH(IL) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the bottom N-channel equation includes an additional term for transition losses. Both top and bottom MOSFET I2R losses are greatest at lowest VIN , and the top MOSFET I2R losses also peak during an overcurrent condition when it is on close to 100% of the period. For most LTC3814-5 applications, the transition loss and I2R loss terms in the bottom MOSFET are comparable, so best efficiency is obtained by choosing a MOSFET that optimizes both RDS(ON) and CMILLER. Since there is no transition loss term in the synchronous MOSFET, however, optimal efficiency is obtained by minimizing RDS(ON) --by using larger MOSFETs or paralleling multiple MOSFETs.
13
LTC3814-5 APPLICATIONS INFORMATION
voltage changes, tie the VOFF pin to a resistive divider from VIN, as shown in Figure 5. Choose the resistor values so that the VRNG voltage equals about 1.55V at the mid-point of VIN as follows: VIN(MAX) + VIN(MIN) R1 VIN,MID = = 1.55V * 1+ 2 R2 With these resistor values, the frequency will remain relatively constant at: 1+ R1/ R2 f= (Hz) ROFF (76pF) for the range of 0.45VIN to 1.55 * VIN , and will be proportional to VIN outside of this range.
1000 1000 1+R1/R2 = 3.2 (VIN,MID = 5V)
Changes in the load current magnitude will also cause a frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By shortening the off-time slightly as current increases, constant-frequency operation can be maintained. This is accomplished with a resistor connected from the ITH pin to the IOFF pin to increase the IOFF current slightly as VITH increases. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 10% of the ROFF current with RITH as shown in Figure 6.
SWITCHING FREQUENCY (kHz)
VIN = 5V
VIN = 24V
SWITCHING FREQUENCY (kHz)
1+R1/R2 = 7.7 (VIN,MID =12V) 1+R1/R2 = 15.5 (VIN,MID = 24V)
VIN = 12V
100 10 100 ROFF (k) 1000
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100 10 100 ROFF (k) 1000
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Figure 4a. Switching Frequency vs ROFF (VOFF = INTVCC)
Figure 4b. Switching Frequency vs ROFF (VOFF Connected to a Resistor Divider from VIN)
VIN R1 VOFF R2 LTC3814-5 VOUT ROFF IOFF 1000pF RITH LTC3814-5 ITH
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RITH =
10ROFF VOUT
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Figure 5. VOFF Connection to Keep the Operating Frequency Constant as the Input Supply Varies
Figure 6. Correcting Frequency Shift with Load Current Changes
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LTC3814-5 APPLICATIONS INFORMATION
Minimum On-Time and Dropout Operation The minimum on-time tON(MIN) is the smallest amount of time that the LTC3814-5 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 350ns. The minimum on-time limit imposes a minimum duty cycle of tON(MIN)/(tON(MIN) + tOFF). If the minimum duty cycle is reached, due to a rising input voltage for example, then the output will rise out of regulation. The maximum input voltage to avoid dropout is: VIN(MAX) = VOUT tOFF tON(MIN) + tOFF The required saturation of the inductor should be chosen to be greater than the peak inductor current: IO(MAX) IL IL(SAT) + 1- DMAX 2 Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool M(R) cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in the front page schematic conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the synchronous MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage. In order for the diode to be effective, the inductance between it and the synchronous MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. Output Capacitor Selection In a boost converter, the output capacitor requirements are demanding due to the fact that the current waveform is pulsed. The choice of component(s) is driven by the acceptable ripple voltage which is affected by the ESR, ESL and bulk capacitance as shown in Figure 8e. The total output ripple voltage is: ESR 1 VOUT =IO(MAX) + f * COUT 1- DMAX where the first term is due to the bulk capacitance and second term due to the ESR.
A plot of maximum duty cycle vs switching frequency is shown in Figure 7.
2.0
SWITCHING FREQUENCY (MHz)
1.5 DROPOUT REGION 1.0
0.5
0 0 0.25 0.50 VIN/VOUT 0.75 1.0
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Figure 7. Maximum Switching Frequency vs Duty Cycle
Inductor Selection An inductor should be chosen that can carry the maximum input DC current which occurs at the minimum input voltage. The peak-to-peak ripple current is set by the inductance and a good starting point is to choose a ripple current of at least 40% of its maximum value: IO(MAX) IL = 40% * 1- DMAX The required inductance can then be calculated to be: VIN(MIN) * DMAX L= f * IL
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LTC3814-5 APPLICATIONS INFORMATION
For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see PC Board Layout Checklist section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 8d. The RMS output capacitor ripple current is: IRMS(COUT) IO(MAX) * VO - VIN(MIN) VIN(MIN) than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Several excellent surge-tested choices are the AVX TPS and TPSV or the KEMET T510 series. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-driven applications providing that consideration is given to ripple current ratings and long term reliability. Other capacitor types include Panasonic SP and Sanyo POSCAPs. In applications with VOUT > 30V, however, choices are limited to aluminum electrolytic and ceramic capacitors.
L D VOUT
VIN
SW
COUT
RL
8a. Circuit Diagram
IIN
IL
8b. Inductor and Input Currents
Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. Manufacturers such as Nichicon, Nippon Chemi-con and Sanyo should be considered for high performance throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance. In surface mount applications, multiple capacitors placed in parallel may be required to meet the ESR, RMS current handling and load step requirements. Dry tantalum, special polymer and aluminum electrolytic capacitors are available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density
ISW tON
8c. Switch Current
ID
tOFF
IO
8d. Diode and Output Currents
VCOUT VOUT (AC) RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP)
VESR
8e. Output Voltage Ripple Waveform
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Figure 8. Switching Waveforms for a Boost Converter
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LTC3814-5 APPLICATIONS INFORMATION
Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous (see Figure 8b). The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10F to 100F A low . ESR capacitor is recommended though not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: IRMS(CIN) = 0.3 * VIN(MIN) L*f * DMAX to approximately VOUT + INTVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1F to 0.47F X5R , or X7R dielectric capacitor is adequate. The reverse breakdown of the external diode, DB, must be greater than VOUT. Another important consideration for the external diode is the reverse recovery and reverse leakage, either of which may cause excessive reverse current to flow at full reverse voltage. If the reverse current times reverse voltage exceeds the maximum allowable power dissipation, the diode may be damaged. For best results, use an ultrafast recovery diode such as the MMDL770T1. IC/MOSFET Driver Supplies (INTVCC) The LTC3814-5 drivers and the LTC3814-5 internal circuits are supplied from the INTVCC pin (see Figure 1). These pins have an operating range between 4.2V and 14V. If the input voltage or another supply is not available in this voltage range, two internal regulators are provided to simplify the generation of this IC/driver supply voltage as described in the next sections. The NDRV Pin Regulator The NDRV pin controls the gate of an external NMOS as shown in Figure 9b and can be used to generate a regulated 5.5V supply from VIN or VOUT. Since the NMOS is external, it can be chosen with a BVDSS or power rating as high as necessary to safely derive power from a high voltage input or output voltage. In order to generate an INTVCC supply that is always above the 4.2V UV threshold, the supply connected to the drain must be greater than 4.2V + RNDRV * 40A + VT. The EXTVCC Pin Regulator A second low dropout regulator is available for voltages 15V. When a supply that is greater than 4.7V is connected to the EXTVCC pin, the internal LDO will regulate 5.5V on INTVCC from the EXTVCC pin voltage and will also disable the NDRV pin regulator. This regulator is disabled when the IC is shut down, when INTVCC < 4.2V, or when EXTVCC < 4.7V.
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Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! Output Voltage The LTC3814-5 output voltage is set by a resistor divider according to the following formula: VOUT = 0.8V 1+ RFB1 RFB2
The external resistor divider is connected to the output as shown in the Functional Diagram, allowing remote voltage sensing. The resultant feedback signal is compared with the internal precision 800mV voltage reference by the error amplifier. The internal reference has a guaranteed tolerance of less than 1%. Tolerance of the feedback resistors will add additional error to the output voltage. 0.1% to 1% resistors are recommended. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VOUT and the BOOST pin rises
17
LTC3814-5 APPLICATIONS INFORMATION
Using the INTVCC Regulators One, both or neither of these regulators can be used to generate the 5.5V IC/driver supply depending on the circuit requirements, available supplies, and the voltage range of VIN or VOUT. Deriving the 5.5V supply from VIN is more efficient, however deriving it from VOUT has the advantage of maintaining regulation of VOUT when VIN drops below the UV threshold. Four possible configurations are shown in Figures 9a through 9d, and are described as follows: 1. Figure 9a. If the VIN voltage or another low voltage supply between 4.5V and 14V is available, the simplest approach is to connect this supply directly to the INTVCC and DRVCC pins. The internal regulators are disabled by shorting NDRV and EXTVCC to INTVCC. 2. Figure 9b. If VIN(MAX) > 14V, an external NMOS connected to the NDRV pin can be used to generate 5.5V from VIN . VIN(MIN) must be > 4.5V + RNDRV * 40A + VT to keep INTVCC above the UV threshold and the BVDSS of the external NMOS must be chosen to be greater than VIN(MAX). The EXTVCC regulator is disabled by grounding the EXTVCC pin. 3. Figure 9c. If the VIN(MAX) < 14.7V and VIN is allowed to fall below 4.2V without disrupting the boost converter operation, use this configuration. The INTVCC supply is derived from VIN until the VOUT > 4.7V. Once INTVCC is derived from VOUT, VIN can fall below the 4V UV threshold without losing regulation of VOUT. Note that in this configuration, VIN must be > ~5V at least long enough to start up the LTC3814-5 and charge VOUT > 4.7V. Also, since VOUT is connected to the EXTVCC pin, this configuration is limited to VOUT < 15V. 4. Figure 9d. Similar to configuration 3 except that VOUT is allowed to be >15V since VOUT is connected to an external NMOS with appropriately rated BVDSS . VIN has same start-up requirement as 3.
VIN
RNDRV NDRV INTVCC LTC3814-5 NDRV
+ + -
4.5V to 14V
INTVCC LTC3814-5
+
5.5V
EXTVCC
EXTVCC
(a) 4.2V to 14V Supply Available
VIN < 14.7V
(b) INTVCC from VIN, VIN > 14V
RNDRV
VOUT VIN < 14.7V
NDRV INTVCC LTC3814-5 5.5V
NDRV INTVCC LTC3814-5
+
+
5.5V
EXTVCC
VOUT 15V
EXTVCC
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(c) INTVCC from VOUT, VOUT 15V
(d) INTVCC from VOUT, VOUT > 15V
Figure 9. Four Possible Ways to Generate INTVCC Supply
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LTC3814-5 APPLICATIONS INFORMATION
Power Dissipation Considerations Applications using large MOSFETs and high frequency of operation may result in a large DRVCC /INTVCC supply current. Therefore, when using the linear regulators, it is necessary to verify that the resulting power dissipation is within the maximum limits. The DRVCC /INTVCC supply current consists of the MOSFET gate current plus the LTC3814-5 quiescent current: ICC = (f)(QG(TOP) + QG(BOTTOM)) + 3mA When using the internal LDO regulator, the power dissipation is internal so the rise in junction temperature can be estimated from the equation given in Note 2 of the Electrical Characteristics as follows: TJ = TA + IEXTVCC * (VEXTVCC - VINTVCC)(38C/W) and must not exceed 125C. Likewise, if the external NMOS regulator is used, the worst case power dissipation is calculated to be: PMOSFET = (VDRAIN(MAX) - 5.5V) * ICC and can be used to properly size the device. FEEDBACK LOOP/COMPENSATION Introduction In a typical LTC3814-5 circuit, the feedback loop consists of two sections: the modulator/output stage and the feedback amplifier/compensation network. The modulator/output stage consists of the current sense component and internal current comparator, the power MOSFET switches and drivers, and the output filter and load. The transfer function of the modulator/output stage for a boost converter consists of an output capacitor pole, RLCOUT, and an ESR zero, RESRCOUT, and also a "right-half plane" zero, (RL /L)(VIN2 / VOUT2). It has a gain/phase curve that is typically like the curve shown in Figure 10 and is expressed mathematically in the following equation. H(s) = VOUT (s) RL * VIN * VSENSE(MAX) = VITH (s) 2.4 * VOUT * RDS(ON) * 1+ s * RESR * COUT 1+ s * RL * COUT (1)
L VOUT 2 * 1 s* * RL VIN2
s = j2 f This portion of the power supply is pretty well out of the user's control since the current sense is chosen based on maximum output load, and the output capacitor is usually chosen based on load regulation and ripple requirements without considering AC loop response. The feedback amplifier, on the other hand, gives us a handle on which to adjust the AC response. The goal is to have an 180 phase shift at DC so the loop regulates and less than 360 phase shift at the point where the loop gain falls below 0dB, i.e., the crossover frequency, with as much gain as possible at frequencies below the crossover frequency. Since the feedback amplifier adds an additional 90 phase shift to the phase shift already present from the modulator/output stage, some phase boost is required at the crossover frequency to achieve good phase margin. The design procedure (described in more detail in the next section) is to (1) obtain a gain/phase plot of modulator/output stage, (2) choose a crossover frequency and the required phase boost, and (3) calculate the compensation network.
180
90 GAIN GAIN (dB) 0 0 PHASE (DEG)
PHASE -90
-180 FREQUENCY (Hz)
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Figure 10. Bode Plot of Boost Modulator/Output Stage
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LTC3814-5 APPLICATIONS INFORMATION
The two types of compensation networks, Type 2 and Type 3 are shown in Figures 11 and 12. When component values are chosen properly, these networks provide a "phase bump" at the crossover frequency. Type 2 uses a single pole-zero pair to provide up to about 60 of phase boost while Type 3 uses two poles and two zeros to provide up to 150 of phase boost. The compensation of boost converters are complicated by two factors: the RHP zero and the dependence of the loop gain on the duty cycle. The RHP zero adds additional phase lag and gain. The phase lag degrades phase margin and the added gain keeps the gain high typically in the frequency region where the user is trying the roll off the gain below 0dB. This often forces the user to choose a crossover frequency at a lower frequency than originally desired. The duty cycle effect of gain (see above transfer function) causes the phase margin and crossover frequency to be dependent on the input supply voltage which may cause problems if the input voltage varies over a wide range since the compensation network can only be optimized for a specific crossover frequency. These two factors usually can be overcome if the crossover frequency is chosen low enough. Feedback Component Selection Selecting the R and C values for a typical Type 2 or Type 3 loop is a nontrivial task. The applications shown in this data sheet show typical values, optimized for the power components shown. They should give acceptable performance with similar power components, but can be way off if even one major power component is changed
C2 GAIN (dB) IN R1 FB RB VREF R2 C1
significantly. Applications that require optimized transient response will require recalculation of the compensation values specifically for the circuit in question. The underlying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. Modulator gain and phase can be obtained in one of three ways: measured directly from a breadboard, or if the appropriate parasitic values are known, simulated or generated from the modulator transfer function. Measurement will give more accurate results, but simulation or transfer function can often get close enough to give a working system. To measure the modulator gain and phase directly, wire up a breadboard with an LTC3814-5 and the actual MOSFETs, inductor and input and output capacitors that the final design will use. This breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the LTC3814-5, no long wires connecting components, appropriately sized ground returns, etc. Wire the feedback amplifier with a 0.1F feedback capacitor from ITH to FB and a 10k to 100k resistor from VOUT to FB. Choose the bias resistor (RB) as required to set the desired output voltage. Disconnect RB from ground and connect it to a signal generator or to the source output of a network analyzer to inject a test signal into the loop. Measure the gain and phase from the ITH pin to the output node at the positive terminal of the output capacitor. Make sure the analyzer's input is AC coupled so that the DC voltages present at both the ITH and VOUT nodes don't corrupt the measurements or damage the analyzer.
IN C3 R1 R3 FB R2 C2 C1 GAIN (dB) PHASE (DEG)
PHASE (DEG)
-6dB/OCT GAIN -6dB/OCT
-6dB/OCT
-
OUT 0
-
OUT 0
GAIN
+6dB/OCT
-6dB/OCT FREQ -90
FREQ -90 PHASE -180 -270 -360
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RB VREF
+
+
PHASE
-180 -270 -360
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Figure 11. Type 2 Schematic and Transfer Function
Figure 12. Type 3 Schematic and Transfer Function
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LTC3814-5 APPLICATIONS INFORMATION
If breadboard measurement is not practical, mathematical software such as MATHCAD or MATLAB can be used to generate plots from the transfer function given in Equation 1. A SPICE simulation can also be used to generate approximate gain/phase curves. Plug the expected capacitor, inductor and MOSFET values into the following SPICE deck and generate an AC plot of VOUT/ VITH with gain in dB and phase in degrees. Refer to your SPICE manual for details of how to generate this plot.
*This file simulates a simplified model of the 3814-5 for generating a v(out)/(vith) or a v(out)/v(outin) bode plot .param vout=24 .param vin=12 .param L=10u .param cout=270u .param esr=.018 .param rload=24 * .param rdson=0.02 .param Vrng=1 .param vsnsmax={0.173*Vrng-0.026} .param K={vsnsmax/rdson/1.2} .param wz={1/esr/cout} .param wp={2/rload/cout} * * Feedback Amplifier rfb1 outin vfb 29k rfb2 vfb 0 1k eithx ithx 0 laplace {0.8-v(vfb)} = {1/(1+s/1000)} eith ith 0 value={limit(1e6*v(ithx),0,2.4)} cc1 ith vfb 100p cc2 ith x1 0.01p rc x1 vfb 100k * * Modulator/Output Stage eout out 0 laplace {v(ith)} = {0.5*K*Rload*vin/vout *(1+s/wz)/(1+s/wp) *(1-s*L/Rload*vout*vout/vin/vin)} rload out 0 {rload} * vstim out outin dc=0 ac=10m; ac stimulus .ac dec 100 10 10meg .probe .end
With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something like Figure 10. Choose the crossover frequency about 25% of the switching frequency for maximum bandwidth. Although it may be tempting to go beyond fSW/4, remember that significant phase shift occurs at half the switching frequency that isn't modeled in the above H(s) equation and PSPICE code. Note the gain (GAIN, in dB) and phase (PHASE, in degrees) at this point. The desired feedback amplifier gain will be -GAIN to make the loop gain at 0dB at this frequency. Now calculate the needed phase boost, assuming 60 as a target phase margin: BOOST = - (PHASE + 30) If the required BOOST is less than 60, a Type 2 loop can be used successfully, saving two external components. BOOST values greater than 60 usually require Type 3 loops for satisfactory performance. Finally, choose a convenient resistor value for R1 (10k is usually a good value). Now calculate the remaining values: (K is a constant used in the calculations) f = chosen crossover frequency G = 10(GAIN/20) (this converts GAIN in dB to G in absolute gain)
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LTC3814-5 APPLICATIONS INFORMATION
TYPE 2 Loop: BOOST + 45 2 1 C2 = 2 * f * G * K * R1 K = tan C1= C2 K R2 = Type 2: A (s) = 1+ s * R3 * C2 s * R1* (C2 + C3) * 1+ s * R3 * C2 * C3 C2 + C3
(
2
1
)
Type 3: A (s) = 1 * s * R1* (C2 + C3)
K 2 * f * C1 V (R1) RB = REF VOUT VREF TYPE 3 Loop: BOOST + 45 4 1 C2 = 2 * f * G * R1 C1= C2 (K 1) K = tan2 K 2 * f * C1 R1 R3 = K1 1 C3 = 2 f K * R3 R2 = V (R1) RB = REF VOUT VREF SPICE or mathematical software can be used to generate the gain/phase plots for the compensated power supply to do a sanity check on the component values before trying them out on the actual hardware. For software, use the following transfer function: T(s) = A(s)H(s) where H(s) was given in equation 2 and A(s) depends on compensation circuit used:
(1+ s * (R1+ R3) * C3) * (1+ s * R2 * C1)
(1+ s * R3 * C3) *
1+ s * R2 * C1* C2 C1+ C2
For SPICE, simulate the previous PSPICE code with calculated compensation values entered and generate a gain/phase plot of VOUT/VOUTIN. Fault Conditions: Current Limit The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3814-5, the maximum sense voltage is controlled by the voltage on the VRNG pin. With peak current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX) RDS(ON) 1 - IL T 2
The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs at the lowest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum.
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LTC3814-5 APPLICATIONS INFORMATION
A reasonable assumption is that the minimum RDS(ON) lies the same percentage below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. Note that in a boost mode architecture, it is only possible to provide protection for "soft" shorts where VOUT > VIN . For hard shorts, the inductor current is limited only by the input supply capability. Run/Soft-Start Function The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC3814-5. Soft-start reduces the input supply's surge current by controlling the ramp rate of the ITH voltage, eliminates output overshoot and can also be used for power supply sequencing. Pulling RUN/SS below 0.9V puts the LTC3814-5 into a low quiescent current shutdown (IQ = 224A). This pin can be driven directly from logic as shown in Figure 14. Releasing the RUN/SS pin allows an internal 1.4A current source to charge up the soft-start capacitor, CSS. When the voltage on RUN/SS reaches 0.9V, the LTC3814-5 turns on and begins ramping the ITH voltage at VITH = VSS - 0.9V. As the RUN/SS voltage increases from 0.9V to 3.3V, the current limit is increased from 0% to 100% of its maximum value. The RUN/SS voltage continues to charge until it reaches its internally clamped value of 4V. If RUN/SS starts at 0V, the delay before starting is approximately: tDELAY,START = 0.9V C = ( 0.64s/F ) CSS 1.4A SS
3.3V OR 5V D1 CSS CSS
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RUN/SS
RUN/SS
Figure 13. RUN/SS Pin Interfacing
Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3814-5 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high input currents. The input current is maximum at maximum output current and minimum input voltage. The average input current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 15mW to 1.5W as the input current varies from 1A to 10A. 2. Transition loss. This loss arises from the brief amount of time the bottom MOSFET spends in the saturated region during switch node transitions. It depends upon the output voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at output voltages above 20V and can be estimated from the second term of the PMAIN equation found in the Power MOSFET Selection section. When transition losses are significant, efficiency can be improved by lowering the frequency and/or using a bottom MOSFET(s) with lower CRSS at the expense of higher RDS(ON). 3. INTVCC current. This is the sum of the MOSFET driver and control currents. Control current is typically
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plus an additional delay, before the current limit reaches its maximum value of: tDELAY,REG 2.4V C 1.4A SS
The start delay can be reduced by using diode D1 in Figure 13.
23
LTC3814-5 APPLICATIONS INFORMATION
about 3mA and driver current can be calculated by: IGATE = f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are the gate charges of the top and bottom MOSFETs. This loss is proportional to the supply voltage that INTVCC is derived from, i.e., VIN, VOUT or an external supply connected to INTVCC. 4. COUT loss. The output capacitor has the difficult job of filtering the large RMS input current out of the synchronous MOSFET. It must have a very low ESR to minimize the AC I2R loss. Other losses, including CIN ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Design Example As a design example, take a supply with the following specifications: VIN = 12V 20%, VOUT = 24V 5%, IOUT(MAX) = 5A, f = 250kHz. Since VIN can vary around the 12V nominal value, connect a resistive divider from VIN to VOFF to keep the frequency independent of VIN changes: R1 12V = - 1= 6.74 R2 1.55V Choose R1 = 133k and R2 = 20k. Now calculate timing resistor ROFF : ROFF = 1+ 133k / 20k = 402.6k 250kHz * 76pF
The duty cycle is: D = 1- 12V = 0.5 24V
and the maximum input current is: IIN(MAX) = 5A = 10A 1- 0.5
Choose the inductor for about 40% ripple current at the maximum VIN: L= 12V 12V 1 = 6H 250kHz * 0.4 * 10A 24V 5A 1 + (4A) = 12A 1- 0.5 2
The peak inductor current is: IL(PEAK) =
so, choose the CDEP147 5.9H inductor with ISAT = 16.4A at 100C. Next, choose the bottom MOSFET switch. Since the drain of the MOSFET will see the full output voltage plus any ringing, choose a 40V MOSFET to provide a margin of safety. The Si7848DP has: BVDSS = 40V RDS(ON) = 9m(max)/7.5m(nom), = 0.006/C, , CMILLER = (14nC - 6nC)/20V = 400pF VGS(MILLER) = 3.5V, JA= 20C/W. This yields a nominal sense voltage of: VSNS(NOM) = 1.7 * 0.0075 * 5A = 128mV 1- 0.5
To guarantee proper current limit at worst-case conditions, increase nominal VSNS by 50% to 190mV. To check if the current limit is acceptable at VSNS = 190mV, assume a
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24
LTC3814-5 APPLICATIONS INFORMATION
junction temperature of about 30C above a 70C ambient (100C = 1.4): IIN(MAX) 190mV 1 - * 4A = 13A 1.4 * 0.009 2 The junction temperature will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in this circuit. Since VIN is always between 4.5V and 14V, it can be connected directly to the INTVCC and DRVCC pins. COUT is chosen for an RMS current rating of about 5A at 85C. The output capacitors are chosen for a low ESR of 0.018 to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only:
VOUT(RIPPLE) = (5A) = 0.25V (about 1%) 1 0.018 + 250kHz * 330F 1 0.5
IOUT(MAX) = IIN(MAX) * (1-DMAX) = 6.5A and double-check the assumed TJ in the MOSFET: 1 PTOP = (6.5A )2 (1.4)(0.009 ) = 1.06W 1 0.5 TJ = 70C + 1.06W * 20C/W = 91C Verify that the Si7848DP is also a good choice for the bottom MOSFET by checking its power dissipation at current limit and minimum input voltage, assuming a junction temperature of 30C above a 70C ambient (100C = 1.4): 6.5A PBOT = 0.5 1 0.5
2
A 0A to 5A load step will cause an output change of up to: VOUT(STEP) = ILOAD * ESR = 5A * 0.018 = 90mV An optional 10F ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 14.
(1.4) (0.009 )
1 6.5A + (24V)2 (2)(400pF) 2 1 0.5 1 1 + (250kHz) 12V 3.5V 3.5V = 1.06W + 0.30W = 1.36W * TJ = 70C + 1.36W * 20C/W = 97C
VOUT ROFF 403k COFF 100pF 1 20k 2 IOFF BOOST LTC3814-5 TG SW PGND BG RUN/SS SGND INTVCC EXTVCC NDRV CC1 47pF SGND RFB1, 29.4k
133k
DB BAS19 16 15 14 13 12 11 10 9 CVCC 1F CDRVCC 0.1F M2 Si7848DP CB 0.1F L1 5.9H
CIN1 68F 20V
VIN CIN2 12V 1F 20V PGND M1 Si7848DP COUT1 330F 35V x 2 VOUT 24V 5A
PGOOD CSS 1000pF
VOFF 3V RNG 4 PGOOD 5 ITH 6 VFB 7 8
D1 B1100
COUT2 10F 50V
CC2 470pF RFB2 1k RC 250k
PGND
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Figure 14. 12V Input Voltage to 24V/5A
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25
LTC3814-5 APPLICATIONS INFORMATION
PC Board Layout Checklist When laying out a PC board follow one of two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. * The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. * Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. * Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3814-5. Use several bigger vias for power components. * Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. * Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. * Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. * Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. * Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. * Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. * Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. * Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and SGND pins. * Connect the top driver boost capacitor CB closely to the BOOST and SW pins. * Connect the bottom driver decoupling capacitor CINTVCC closely to the INTVCC and PGND pins.
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LTC3814-5 PACKAGE DESCRIPTION
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
2.74 (.108)
4.90 - 5.10* (.193 - .201) 2.74 (.108) 16 1514 13 12 1110 9
6.60 0.10 4.50 0.10
SEE NOTE 4
2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC 2.74 6.40 (.108) (.252) BSC
RECOMMENDED SOLDER PAD LAYOUT
12345678 1.10 (.0433) MAX
0 - 8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3814-5 TYPICAL APPLICATION
24V Input Voltage to 50V/5A
VIN 143k COFF 100pF 1 10k 100k PGOOD CSS 1000pF 2 IOFF BOOST VOUT ROFF 806k RNDRV 100k M3 ZXMN10A07F DB BAS19 16 CB 0.1F LTC3814-5 15 VOFF TG 3 14 VRNG SW 4 PGOOD 13 5 PGND ITH 6 VFB 12 BG 7 11 INTVCC RUN/SS 8 10 SGND EXTVCC 9 NDRV SGND RFB1 30.9k
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CIN1 68F 50V
CIN2 1F 50V PGND
VIN 12V* TO 40V
150k
L1 10H
M1 Si7850DP CDRVCC 0.1F COUT1 220F 63V x2
VOUT 50V 5A
M2 Si7850DP
D1 B1100
COUT2 10F 100V x2
CC2 330pF RFB2 499 RC 300k
CC1 150pF
CVCC 1F
PGND
*IOUT(MAX) = 2A AT VIN = 12V
RELATED PARTS
PART NUMBER LTC1624 LTC1700 LTC1871/LTC1871-7 LTC1872/LTC1872B LT 1930 LT1931 LTC3401/LTC3402 LTC3703/LTC3703-5 LTC3704 LT3782 LTC3803/LTC3803-5 LTC3813 LTC3872 LTC3873
(R)
DESCRIPTION Current Mode DC/DC Controller No RSENSETM Synchronous Step-Up Controller No RSENSE, Wide Input Range DC/DC Boost Controller SOT-23 Boost Controller 1.2MHz, SOT-23 Boost Converter Inverting 1.2MHz, SOT-23 Converter 1A/2A 3MHz Synchronous Boost Converters 100V Synchronous Controller Positive-to Negative DC/DC Controller 2-Phase Step-Up DC/DC Controller 200kHz Flyback DC/DC Controller 100V Current Mode Synchronous Step-Up Controller No RSENSE Current Mode Boost DC/DC Controller No RSENSE Constant-Frequency Boost/Flyback/SEPIC Controller
COMMENTS SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V Up to 95% Efficiency, Operating as Low as 0.9V Input No RSENSE, Current Mode Control, 2.5V VIN 36V Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode Up to 34V Output, 2.6V VIN 16V, Miniature Design Positive-to Negative DC/DC Conversion, Miniature Design Up to 97% Efficiency, Very Small Solution, 0.5V VIN 5V Step-Up or Step Down, 600kHz, SSOP-16, SSOP-28 No RSENSE, Current Mode Control, 50kHz to 1MHz High Power Boost with Programmable Frequency, 150kHz to 500kHz, 6V VIN 40V Optimized for Driving 6V MOSFETs ThinSOT Large 1 Gate Drivers, No Current Sense Resistor Required 550kHz Fixed Frequency, 2.75V VIN 9.8V VIN and VOUT Limited Only by External Components
No RSENSE is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0408 REV B * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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